Electronic circuit designs can be constructed, simulated, debugged, and translated into electronic hardware using software-based implementation tools. An implementation tool, such as a High Level Modeling System (HLMS), can provide blocks that can be combined to build an electronic circuit. A block, also called a module, refers to a high level software construct that represents a particular circuit function, such as multiplexing, addition, multiplication, or the like. Blocks may have ports that can produce and consume signals, and may be arranged within the implementation tool to form a circuit and/or system. Communication among the blocks can be represented by wires, or signals, that graphically link the blocks.
The circuit design may be simulated within the implementation tool once it is constructed. Some implementation tools can generate a hardware implementation from the block representation of the circuit design. For example, an implementation tool may generate the bitstream necessary to program a programmable logic device (PLD) or generate the hardware description language (HDL) files necessary to specify the hardware design.
One example of an HLMS is System Generator for DSP™, available from Xilinx, Inc. of San Jose, Calif. System Generator for DSP™ is a system level modeling tool that facilitates field programmable gate array (FPGA) hardware design. System Generator for DSP™ provides a wide range of blocks that can be automatically compiled into a design suitable for an FPGA. Among these blocks are high level abstractions that implement complex functions, including digital signal processing as well as communication and control logic. In addition, access to underlying FPGA resources can be provided through low level block abstractions that facilitate the construction of highly efficient FPGA designs. (Xilinx and System Generator for DSP are trademarks of Xilinx, Inc. in the United States, other countries, or both).
An FPGA is one variety of PLD that typically includes an array of functional elements such as configurable logic blocks (CLBs), which may be surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a programmable interconnect structure. The CLBs, IOBs, and interconnect structure can be programmed by loading a stream of configuration data, referred to as a bitstream, into internal configuration memory cells that define how the CLBs, IOBs, and interconnect structure are configured. An FPGA may also include various other functional elements such as memories, microprocessors, digital clock managers (DCMs), input/output (I/O) transceivers, and the like.
In order to implement a design on an FPGA, the design, which typically is specified using an HDL, must be mapped onto the available functional elements of the FPGA device. That is, the circuit design elements, such as logic gates and the like, must be mapped onto the functional elements, e.g., lookup-tables (LUTs), CLBs, flip-flops, block random access memories (BRAMs), IOBs, and the like, available on the physical FPGA device within which the circuit design will be implemented. Once the elements of the circuit design are mapped to functional elements, the circuit design must be placed. Placement refers to the process of assigning a site, or physical location on the FPGA, to each element of the circuit design. After placement, the circuit design can be routed. A bitstream then can be generated which, when loaded into the PLD, implements the circuit design within the device.
The above processes can be performed by an implementation tool such as an HLMS. With respect to placement, for example, a placement algorithm can be executed by the implementation tool that assigns locations to the elements of the circuit design based upon various factors such as timing constraints and the particular functional element of the FPGA to which each design element is mapped. Most implementation tools utilize a placement algorithm that relies upon a global cost function. The global cost function seeks to minimize the wire lengths and delays across all connections of the circuit design. In other words, the implementation tool evaluates placement of circuit components by applying a cost function to the circuit design as a whole, not with a view toward any individual connection.
There are cases, however, in which global placement techniques are ineffective. In those cases, a select group of connections may require special handling. For example, the connection between a BRAM and a flip flop may require a very small delay. A conventional implementation tool may determine a placement for the BRAM and flip flop that does not meet the needed timing requirements for that connection. In that case, the critical connection fails timing requirements. There may be only a very limited number of placement configurations, or even a single one, for the BRAM and flip flop that meets the timing requirement. A placement algorithm that is guided by a global cost function may not find this placement for a specific connection. In such cases, it becomes necessary for the designer to intervene by creating a relatively placed macro (RPM).
An RPM refers to a grouping of two or more circuit primitives which have been associated with location constraints. The location constraints define relative coordinates among the various members of the RPM, thereby allowing the RPM to be treated as a single, larger component. The constraints can be specific or more generalized. For example, an RPM may specify that a circuit element “A” and a circuit element “B” must be located within the same slice of a CLB, or at particular sites of the same CLB, to ensure that a timing requirement between elements “A” and “B” is met. In another example, an RPM can specify that another circuit element “C” must be placed in a column of the FPGA that is adjacent to the column within which elements “A” and “B” are placed.
The implementation tools abide by the constraints imposed by RPMs when placing a circuit design. RPMs, however, must be manually created by a circuit designer, typically in response to a placement that does not address the timing needs of one or more specific connections of the circuit design.